Gate Stack and Silicide Issues in Silicon Processing Symposium Held April 25-27, 2000, San Francisco, California, U.S.A

As we move into the 21st century, the feature size of microelectronic devices is approaching the deep submicron regime. At these dimensions, the process development and integration issues related to gate stack and silicide processing are key challenges. Gate leakage is rising sharply due to direct tunneling. Power and reliability concerns are both expected to limit the ultimate scaling of SiO2-based insulators to about 1.5nm. New gate insulators must not deleteriously affect the interface quality, thermal stability, charge trapping, or process integration. New metal gate materials and damascene gates are being seriously investigated, perhaps in conjunction with the application of a high-permittivity gate insulator, to provide sufficient device performance at ULSI dimensions. The silicidation process is also coming under very strong pressure. Narrow device widths and decreasing junction depths are making the formation of low-leakage, low-resistance silicide straps extremely difficult. Producingshallower junctions via ion implantation is inhibited by transient enhanced diffusion and low beam currents at low implantation energies. Gate stack and contact film effects, such as point defect injection, extended defect formation, and stress on ultrashallow junction formation must be considered. This is the first MRS symposium volume dedicated solely to these issues.Clevenger, L. is the author of 'Gate Stack and Silicide Issues in Silicon Processing Symposium Held April 25-27, 2000, San Francisco, California, U.S.A' with ISBN 9781558995192 and ISBN 1558995196.