8390838
9783639185546
Design and Modeling of PLL Based CDR for Inter Chip Communications: Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery Integrated ... Gb/s Intra/Inter Chip Communications in SoC
by Assaad, Maher
31245
List Price
Discount
36% Off
You Save
$31.64
About this item
- Condition: New
- Provider: LightningBooks Contact
- Provider Rating: 85%
- Ships From: Multiple Locations
- Shipping: Standard, Expedited (tracking available)
- Comments: Fast shipping! All orders include delivery confirmation.
Product details
- ISBN-13: 9783639185546
- ISBN: 3639185544
- Publication Date: 2009
- Publisher: VDM Verlag Dr. Mueller e.K.
AUTHOR
SUMMARY
Assaad, Maher is the author of 'Design and Modeling of PLL Based CDR for Inter Chip Communications: Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery Integrated ... Gb/s Intra/Inter Chip Communications in SoC', published 2009 under ISBN 9783639185546 and ISBN 3639185544.
[read more]
The ValoreBooks Guarantee
With our dedicated customer support team, you can rest easy knowing that we're doing everything we can to save you time, money, and stress.
